The present invention relates to a semiconductor memory device; and, more particularly, to the semiconductor memory device for controlling a bit line sense amplifier.
Semiconductor memory devices such as a Dynamic Random Access Memory (DRAM) are required to operate faster and be more highly integrated. As semiconductor memory devices operate faster, it is more difficult to maintain margins for operation.
A semiconductor memory device includes a differential bit line pair, i.e., a bit line and a bit line bar. When a word line is activated in response to a row address, data in a plurality of memory cells connected to the word line are transmitted to respective bit line pairs. A bit line sense amplifier senses and amplifies a voltage difference between the differential bit line pair. Data stored in the memory cells are read by the bit line sense amplifier.
FIG. 1 illustrates a block diagram of a conventional synchronous DRAM (SDRAM). The conventional SDRAM includes an input buffer/command decoder 11, a row control unit 12 and a column control unit 13. The input buffer/command decoder 11 buffers a clock CLK, commands /CS, /RAS, /CAS and /WE, and address signals A<0:i> and decodes the commands /CS, /RAS, /CAS and /WE. The input buffer/command decoder 11 outputs row command signals such as a refresh command signal REF, an active command signal ACT and a precharge command signal PRE, and column command signals such as a read command signal RD and a write command signal WT. The row control unit 12 generates row pre-decoding signals RA<0:k> and sense amplifier enabling signals SAEN<0:j> in response to the row command signals and the address signals A<0:i>. The column control unit 13 generates column pre-decoding signals CA<0:1> in response to the column command signals and the address signals A<0:i>.
The conventional SDRAM further includes a plurality of memory cell arrays 18, a plurality of bit line sense amplifier (BLSA) arrays 19, a column decoder 16, row decoders 15 and sense amplifier controllers 17. Each memory cell array and BLSA array are arranged alternately. The column decoder 16, receiving the column pre-decoding signals CA<0:1>, activates a column selecting signal YS corresponding to each column. The row decoders 15, receiving the row pre-decoding signals RA<0:k> and the sense amplifier enabling signals SAEN<0:j>, select one of word lines WL0 to WLk. The sense amplifier controllers 17 control the BLSA arrays 19 in response to the sense amplifier enabling signals SAEN<0:j>.
Each BLSA array operates corresponding to its upper/lower memory cell arrays. The BLSA array is controlled by the sense amplifier enabling signals corresponding to both memory cell arrays.
FIG. 2 illustrates a schematic circuit diagram of the BLSA array and the sense amplifier controller described in FIG. 1. The BLSA array 19-1 includes a plurality of bit line sense amplifiers. Each bit line sense amplifier includes an upper bit line switching unit 23, a sense amplifier 24, a bit line equalizing/precharging unit 25 and a lower bit line switching unit 26. The sense amplifier controller 17-1 includes a sense amplifier supply line driver 22 and a driving control signal generator 21.
The sense amplifier 24 has a latch structure wherein two pull-up PMOS transistors and two pull-down NMOS transistors are cross-connected. The two pull-up PMOS transistors are connected to a pull-up supply line, i.e., a RTO line, on the other side. The two pull-down NMOS transistors are connected to a pull-down supply line, i.e., a SB line, on the other side. The RTO line and the SB line are enabled at predetermined voltage levels in response to the sense amplifier enabling signal SAEN<n>. The sense amplifier 24 senses the voltage difference of the bit line pair, which share charges and have fine voltage difference. The sense amplifier 24 amplifies the bit line pair to a ground voltage VSS and a core voltage VCORE respectively.
The upper bit line switching unit 23 and the lower bit line switching unit 26 each include two NMOS transistors. The upper bit line switching unit 23 determines whether a bit line pair in the upper memory cell array 18-1 is connected to the sense amplifier 24, according to an upper bit line switching signal SHL. The lower bit line switching unit 26 determines whether a bit line pair in the lower memory cell array 18-2 is connected to the sense amplifier 24, according to a lower bit line switching signal SHR.
The bit line equalizing/precharging unit 25 includes three NMOS transistors. The bit line equalizing/precharging unit 25 equalizes and precharges the bit line pair with bit line precharge voltage VBLP in response to a bit line equalizing signal BLEQ.
The sense amplifier supply line driver 22 includes two NMOS transistors. The first NMOS transistor supplies the RTO line with the core voltage VCORE in response to a RTO line driving signal SAP. The second NMOS transistor supplies the SB line with the ground voltage VSS in response to a SB line driving signal SAN.
The driving signal generator 21 includes a plurality of inverters, which delay the sense amplifier enabling signal SAEN<n> and generate the RTO line driving signal SAP and the SB line driving signal SAN.
FIG. 3 illustrates a signal timing diagram of the SDRAM described in FIG. 1. The row pre-decoding signal RA is activated in response to the active command signal ACT. The word line in the memory cell array corresponding to the row pre-decoding signal RA is enabled. The charges stored in cell capacitors are transmitted to the bit line pair. This results in a fine voltage difference between the bit line pair.
After a predetermined delay time from an input of the active command signal ACT, the sense amplifier enabling signal SAEN<n> is activated. In response to SAEN<n>, the RTO line driving signal SAP and the SB line driving signal SAN are activated. The two NMOS transistors in the sense amplifier supply line driver 22 supply the RTO and the SB lines with the core voltage VCORE and the ground voltage VSS respectively. For example, in case that the value ‘1’ is stored in the memory cell, the bit line BL is amplified to the level of core voltage VCORE corresponding to the value ‘1’. The bit line bar /BL is amplified to the level of ground voltage corresponding to the value ‘0’.
Thereafter, the column pre-decoding signal CA is activated in response to the read command signal RD. If the column selecting signal YS is activated, the value stored in the bit line pair is output through a data bus.
Likewise, the column pre-decoding signal CA is activated in response to the write command signal WT. If the column selecting signal YS is activated, the value stored in the data bus is transmitted to the bit line pair.
After the value stored in the bit line pair is transmitted to the memory cell, the word line is inactivated in response to the precharge command signal PRE. The sense amplifier 24 is disabled according to inactivation of the sense amplifier enabling signal SAEN<n>. The bit line pair is equalized and precharged to the level of the bit line precharge voltage VBLP.
However, for a writing operation of a value having an opposite value as compared with the value stored in the memory cell, the value latched in the sense amplifier 24 is required to be inversely amended. Accordingly, such a writing operation takes more time as compared with a writing operation of a value having an identical value. The characteristics of write recovery time tWR are deteriorated, particularly in a low power semiconductor memory device.
If a driver for delivering a value into a unit cell during the writing operation is expanded in order to operate fast, the speed of the writing operation is improved. Meanwhile, current consumption increases exponentially.